Computer Science · Topic 3 · Hardware — the CPU
Fetch. Decode. Execute.
Step through a real program one register-transfer at a time. Watch the PC, MAR, MDR, CIR and ACC do exactly what the von Neumann architecture says they should — the single most-asked diagram in Paper 1.
0478 Topic 3 — Hardware
von Neumann · registers · buses · FDE cycle
Controls
1.5
PC
0
MAR
–
MDR
–
CIR
–
ACC (accumulator)
0
Register-transfer log
— nothing yet — press Step
📋 The registers (Cambridge)
- PC (program counter) — holds the address of the NEXT instruction to fetch.
- MAR (memory address register) — holds the address currently being read from or written to.
- MDR (memory data register) — holds the data/instruction just transferred to or from memory.
- CIR (current instruction register) — holds the instruction being decoded and executed.
- ACC (accumulator) — holds the result of calculations done by the ALU.
🔁 The cycle, step by step
- Fetch: PC → MAR; memory at that address → MDR; MDR → CIR; PC is incremented.
- Decode: the control unit works out what the instruction in the CIR means.
- Execute: the instruction is carried out (e.g. ALU adds, a value is stored, or the PC is changed for a jump).
- The address bus carries addresses (one direction); the data bus carries data (both directions).
🎯 Syllabus reference (0478)
- Topic 3 — Hardware: the role of the CPU; von Neumann architecture — ALU, control unit, registers (PC, MAR, MDR, CIR, ACC) and buses; describe each stage of the fetch–decode–execute cycle.